1. Field of the Invention
The present invention is directed generally to an input circuit to be used, for example, in a memory device, and a method for operating the input circuit and memory device. More particularly, the present invention is directed to an input circuit and method that eliminates idle cycles in a memory device through the use of input registers.
2. Description of the Background
Memory devices, such as static random access memories (SRAMs), typically include a memory array for storing data, an address circuit for accessing the memory array, a write circuit for writing data to the memory array, and a read circuit for reading data from the memory array. In pipelined memory devices, data is typically read from a memory array during one clock cycle and provided on the data bus during the next clock cycle. Similarly, data to be written to a memory array is typically latched from the data bus during one clock cycle and written to the memory array during the next clock cycle. As a result, in a pipelined memory device a read operation followed by a write operation will typically require that the memory device be idle for at least one clock cycle while a previous operation is completed and the next operation is begun. Those idle cycles can significantly reduce the operating speed of a memory device.
Thus, the need exists for a pipelined memory device in which idle cycles during data transfers to and from the memory device are eliminated.